An interrupt is a mechanism that temporarily pauses the main program execution to respond to important events—like a timer overflow, data from a sensor, or a button press.
Types of Interrupts in ARM
| Type | Trigger Source | Description |
|---|---|---|
| IRQ (Interrupt Request) | From general peripherals (e.g., timers, UART) | Normal priority interrupt |
| FIQ (Fast Interrupt Request) | From high-speed peripherals (e.g., DMA) | Highest priority interrupt (fastest response) |
| SWI (Software Interrupt) | Triggered by SWI instruction | Used by software to enter a system or kernel mode |
Assigning Interrupts:
It means deciding which hardware component (like timer, UART, DMA) should be allowed to trigger which type of interrupt (IRQ or FIQ).
How is this assignment done?
- Through hardware: Using an Interrupt Controller which receives multiple interrupt signals and forwards them to the CPU as either IRQ or FIQ.
- Through software: Programmers can configure interrupt sources via registers during system initialization.
Common Design Practice:
| Interrupt Type | Common Use Case | Priority |
|---|---|---|
| SWI | OS calls (privileged operations) | Software-triggered |
| IRQ | General-purpose events like timers | Medium |
| FIQ | Very fast, time-critical tasks like DMA | Highest |
FIQ is usually reserved for one very important peripheral, while IRQ handles multiple general tasks.
Interrupt Latency
The time delay between when an interrupt is raised and when the processor starts executing the ISR (Interrupt Service Routine).
⏱️ Why it’s important:
In real-time systems (like medical devices or robots), even a tiny delay in responding to interrupts can be dangerous.
Factors Affecting Interrupt Latency
- Hardware delay: How fast the CPU detects the interrupt.
- Software delay: Includes:
- Time to save context (registers)
- Time to jump to ISR
- Time due to disabled interrupts
- Interrupt priority handling
Techniques to Reduce Interrupt Latency
1. Nested Interrupts
- Allows higher-priority interrupts to interrupt a currently running ISR.
- Example:
- Timer interrupt (IRQ) is being serviced.
- A fast DMA interrupt (FIQ) occurs → CPU temporarily pauses IRQ ISR, handles FIQ, and then returns to IRQ.
- Implemented by:
- Re-enabling interrupts early inside ISR (after servicing the source).
2. Interrupt Prioritization
- Using an Interrupt Controller, assign priority levels to each interrupt.
- While handling a low-priority interrupt, only allow higher-priority ones to interrupt.
- Example:
- UART interrupt (priority 1)
- Timer interrupt (priority 2)
- DMA interrupt (priority 3 — highest)
So if DMA triggers during UART ISR, the DMA is handled immediately.
