The Current Program Status Register (CPSR) is a 32-bit register in ARM architecture used to:
- Monitor internal processor status
- Control processor modes, interrupt states, and execution states
- Hold condition flags for conditional execution
It plays a central role in managing instruction execution, mode switching, and interrupt handling.
Layout of CPSR
The CPSR is divided into four 8-bit fields:
| Bits | Field | Description |
|---|---|---|
| [31:24] | Flags | Stores condition flags (N, Z, C, V, Q) and state bits (J, T) |
| [23:16] | Status | Reserved for future use |
| [15:8] | Extension | Reserved for future expansion |
| [7:0] | Control | Stores interrupt masks, processor state, and processor mode bits |
The status and extension fields are generally unused in current ARM implementations.
Processor Modes in CPSR
ARM supports 7 processor modes, each with different access permissions:
| Mode Name | Abbrev. | Privileged? | CPSR Mode Bits | Hex |
|---|---|---|---|---|
| User | usr | ❌ No | 10000 | 0x10 |
| FIQ | fiq | ✅ Yes | 10001 | 0x11 |
| IRQ | irq | ✅ Yes | 10010 | 0x12 |
| Supervisor | svc | ✅ Yes | 10011 | 0x13 |
| Abort | abt | ✅ Yes | 10111 | 0x17 |
| Undefined | und | ✅ Yes | 11011 | 0x1B |
| System | sys | ✅ Yes | 11111 | 0x1F |
Privileged modes can read/write all parts of CPSR.
User mode has limited access—read-only to some parts.
Banked Registers and Mode Switching
- ARM has 37 physical registers, but only a subset is visible at any time.
- Some registers are banked — unique to each mode.
- Example:
- r13_usr and r14_usr (User mode)
- r13_irq and r14_irq (IRQ mode)
When the processor switches mode (e.g., on interrupt), it:
- Banks (hides) the user registers
- Replaces them with mode-specific registers (e.g., r13_irq, r14_irq)
- Saves the current CPSR into SPSR_mode (Saved Program Status Register)
Only privileged modes have access to the SPSR.
Processor States and Instruction Sets
CPSR determines which instruction set is active:
| Bits | Instruction Set | Description |
|---|---|---|
| J = 0, T = 0 | ARM | 32-bit instructions |
| J = 0, T = 1 | Thumb | 16-bit instructions |
| J = 1, T = 0 | Jazelle | 8-bit Java bytecodes (specialized) |
State is changed using special branch instructions, not by mixing instructions.
Interrupt Mask Bits in CPSR
The CPSR controls the enabling/disabling of interrupts using I and F bits:
| Bit | Name | Function |
|---|---|---|
| 7 | F | 1 = Mask FIQ (Fast Interrupt Request) |
| 6 | I | 1 = Mask IRQ (Interrupt Request) |
🔹 Set to 1 → Disable
🔹 Set to 0 → Enable
Condition Flags in CPSR
Located in bits [31:28], these flags are modified by ALU operations with S suffix (e.g., ADDS, SUBS):
| Flag | Name | Set When |
|---|---|---|
| N | Negative | Result is negative (bit 31 = 1) |
| Z | Zero | Result is zero |
| C | Carry | Unsigned carry-out from result |
| V | Overflow | Signed overflow in result |
| Q | Saturation | Overflow/saturation in DSP instruction (sticky flag, manual reset) |
Conditional Execution in ARM
Most ARM instructions can be executed conditionally based on CPSR condition flags.
| Condition | Mnemonic | Meaning |
|---|---|---|
| EQ | Equal | Z = 1 |
| NE | Not Equal | Z = 0 |
| CS/HS | Carry Set | C = 1 |
| CC/LO | Carry Clr | C = 0 |
| MI | Minus | N = 1 |
| PL | Plus | N = 0 |
| VS | Overflow | V = 1 |
| VC | No OVFL | V = 0 |
| AL | Always | Default |