**Analog Electronic Circuits Previous year solved Question Paper**

#### MODULE 1

1.Derive an expression for S_{Ico} and S_{VB} of collector to base bias circuit.

2. Design a suitable Clipper circuit to the output shown in Fig Q2. Assume silicon diode.

3. Find I_{c}, V_{E}, V_{B}, V_{C} and V_{CE} for the circuit shown in Fig Q3. Assume silicon transistor with **β**=60.

4. Explain how a transistor can be used as a switch.

5. Determine I_{E}, I_{B}, V_{CE}, V_{CB}, V_{C}, and V_{E} for the network shown in Fig Q5. Assume silicon transistor with β = 60.

6. Determine V_{o} for the network shown in Fig Q6 the frequency of i/p signal is 1KHz. Assume ideal diode.

7. Draw a double ended clipper circuit and explain the working principle with transfer characteristics.

8. Draw and explain the working of clamper circuit which clamps the positive peak of a signal to zero.

9. Derive the expression for stability factors S’ and S” for fixed bias circuit.

10. A voltage divider biased circuit has R₁ = 39KΩ, R_{2} = 82KΩ, R_{C} = 3.3KΩ, R_{E} = 1KΩ and V_{cc} = 18V. The silicon transistor or used has β = 120. Find Q-point and stability factor.

11. Explain the operation of transistor as switch with suitable circuit and necessary waveforms.

**MODULE 2**

1.For the network shown in Fig Q1 determine z_{i}, z_{o}, A_{v} and A_{I}

2. Derive an expression for z_{i}, z_{o}, A_{v} for emitter follower configuration using approximate hybrid model.

3. Obtain the expression for Miller i/p capacitance.

4. Draw the complete hybrid equivalent model of a transistor. Derive an expression for z_{i}, z_{o}, A_{I} and A_{v}

5. For the common base amplifier shown in Fig Q5 ,determine: i) z_{i} ii) A_{I} iii) A_{v}. Give hie = 1.6kΩ, hfe = 110, hre = 2×10^{-4}, hoe = 20µA/v.

6. State and prove Millers theorem.

7. Compare the characteristics of CB, CE and CC configurations.

8. For the collector feedback configuration having R_{F} = 180KΩ, R_{C} = 2.7KΩ, C_{l} = 10*µ*F, C_{2} = 10µF, β = 200 , r_{o}=∞Ω and V_{cc} = 9volts. Determine the following parameters: i) re ii) z_{i} iii) z_{o} iv) A_{v}

iii) zo

9. Derive suitable expression to explain the effect of cascading of amplifiers on lower and upper cut off frequencies.

10. Derive equations for miller input capacitance and miller output capacitance.

11. A transistor in CE mode has h-parameters h_{ie} = 1.1KΩ, h_{re} = 2 x10_{-4} , h_{fc} = 100 and h_{oe}=25µA/V. Determine the equivalent CB parameters.

**MODULE 3**

1.For the Darlington emitter, follower shown in Fig Q1.

i) Calculate the de-bias voltages V_{B}, V_{E} , V_{C} and currents I_{B} and I_{C}

ii) Calculate the i/p and o/p impedances

iii) Determine the voltage and current gains

iv) The ac o/p voltage for V_{i} = 120mV

2. For the cascaded arrangement shown in Fig Q2 calculate :

- i) The loaded voltage gain of each stage
- ii) The total gain of the system A
_{V}and A_{V1} - iii) The loaded current gain of each stage
- iv) The total current gain of the system.

3. List the advantages of negative feedback.

4. Derive an expression for input resistance of current series and current shunt feedback amplifier.

5. Negative feedback to be used to reduce noise from an amplifier by 90% i) what mast the percentage negative feedback to accomplish this, if the initial voltage gain is 50? ii) What will be the voltage gain with feedback.

6. Derive expression for Zi and Ai for a Darlington Emitter follower circuit.

7. Explain the need of a cascading amplifier. Draw and explain the block diagram of two stage cascade amplifier.

8. Write a note on cascade amplifier.

9. List the general characteristics of negative feedback amplifier.

10. A given amplifier arrangement has the following voltage gain AV_{1} = 10, AV₂ = 20 and AV_{3} = 40. Calculate the overall voltage gain and determine the total voltage gain in dBS.

11. For the voltage series feedback amplifier. Derive an expression for output impedance (Resistance).

**MODULE 4**

1.Derive an expression for frequency of oscillation of RC phase shift oscillator.

2. With a neat circuit diagram, explain the working of complementary class B power amplifier.

3. The following distortion readings are available for a power amplifier. D_{2} = 0.2 , D_{3} = 0.02, D_{4} = 0.06 with I_{1} = 3.3A and R_{C} = 4Ω

i) Calculate THD ii) Determine the fundamental power iii) calculate the total power

4. With a neat circuit diagram, explain the working of Hartley oscillator.

5. For a class B amplifier providing a 20V peak signal to a 16Ω load and a power supply of V_{CC} =30V determine the i/p power, o/p power and efficiency.

6. Explain the classification of power amplifier based on Q- point.

7. Show that maximum efficiency of class-B push pull amplifier (power amplifier) circuit is 78.54%.

8. Explain the classification of power amplifier with a neat circuit diagram and waveforms.

9. A class-B push pull amplifier operating with V_{cc} = 25V provides a 22V peak signal to 8Ω load. Calculate the circuit efficiency and power dissipated per transistor.

10. Draw the circuit of wein bridge oscillator and explain its operation.

11. With a neat circuit diagram and waveform, explain the working principal of crystal oscillator operating in series resonant mode. A crystal has the following parameters L = 0.334H, C=0.065pF and R = 5.5KΩ. Calculate its resonant frequency.

**MODULE 5**

1.Draw the circuit a fixed bias JFET amplifier and its equivalent circuit. Hence obtain the expression Z_{in}, Z_{o }and A_{v}.

2. A JFET has device parameter of g_{mo} = 10m℧ and I_{pss} = 12mA. When the device is suitably biased, the drain current was found to be 8mA. Determine: i) V_{p} ii) g_{m} iii) V_{GS}

3. Give the comparison of FET over BJT.

4. With a neat sketch, explain the construction and working principle of N-channel enhancement type MOSFET and also explain its static drain characteristics.

5. Obtain the expression for trans conductance gm of JFET.

6. For the voltage divider bias configuration shown in Fig Q6. Determine the value of R_{s}, if VD = 12V and V_{GSQ} = -2V.

7. With the help of neat diagram, explain the working and characteristics of N-channel JFET.

8. For a self bias JFET circuit, V_{DD} = +12V, R_{D} = 2.2KΩ, R_{G} = 1MΩ, R_{S} = 1KΩ, I_{DSS} = 8mA, V_{p}= -4 Volts. Determine the following parameters: i)V_{GS} ii) I_{D} iii) V_{DS} iv) V_{s} v) V_{G} vi) V_{D}

9. With neat sketches, explain the operation and characteristics of n-channel depletion type MOSFET.

10. Derive expression for V_{GS}, I_{D}, V_{DS}, V_{D} and V_{S} for a voltage divider bias circuit using FET.