Analog Electronic Circuits Previous year solved Question Paper

Analog Electronic Circuits Previous year solved Question Paper

MODULE 1

1.Derive an expression for S_Ico and S_VB of collector to base bias circuit.

2. Design a suitable Clipper circuit to the output shown in Fig Q2. Assume silicon diode.

3. Find I_c, V_E, V_B, V_C and V_CE for the circuit shown in Fig Q3. Assume silicon transistor with β=60.

4. Explain how a transistor can be used as a switch.

5. Determine I_E, I_B, V_CE, V_CB, V_C, and V_E for the network shown in Fig Q5. Assume silicon transistor with β = 60.

6. Determine V_o for the network shown in Fig Q6 the frequency of i/p signal is 1KHz. Assume ideal diode.

7. Draw a double ended clipper circuit and explain the working principle with transfer characteristics.

8. Draw and explain the working of clamper circuit which clamps the positive peak of a signal to zero.

9. Derive the expression for stability factors S’ and S” for fixed bias circuit.

10. A voltage divider biased circuit has R₁ = 39KΩ, R₂ = 82KΩ, R_C = 3.3KΩ, R_E = 1KΩ and V_cc = 18V. The silicon transistor or used has β = 120. Find Q-point and stability factor.

11. Explain the operation of transistor as switch with suitable circuit and necessary waveforms.

MODULE 2

1.For the network shown in Fig Q1 determine z_i, z_o, A_v and A_I

2. Derive an expression for z_i, z_o, A_v for emitter follower configuration using approximate hybrid model.

3. Obtain the expression for Miller i/p capacitance.

4. Draw the complete hybrid equivalent model of a transistor. Derive an expression for z_i, z_o, A_I and A_v

5. For the common base amplifier shown in Fig Q5 ,determine: i) z_i ii) A_I iii) A_v. Give hie = 1.6kΩ, hfe = 110, hre = 2×10^-4, hoe = 20µA/v.

6. State and prove Millers theorem.

7. Compare the characteristics of CB, CE and CC configurations.

8. For the collector feedback configuration having R_F = 180KΩ, R_C = 2.7KΩ, C_l = 10µF, C₂ = 10µF, β = 200 , r_o=∞Ω and V_cc = 9volts. Determine the following parameters: i) re ii) z_i iii) z_o iv) A_v
iii) zo

9. Derive suitable expression to explain the effect of cascading of amplifiers on lower and upper cut off frequencies.

10. Derive equations for miller input capacitance and miller output capacitance.

11. A transistor in CE mode has h-parameters h_ie = 1.1KΩ, h_re = 2 x10^_-4 , h_fc = 100 and h_oe=25µA/V. Determine the equivalent CB parameters.

MODULE 3

1.For the Darlington emitter, follower shown in Fig Q1.

i) Calculate the de-bias voltages V_B, V_E , V_C and currents I_B and I_C
ii) Calculate the i/p and o/p impedances
iii) Determine the voltage and current gains
iv) The ac o/p voltage for V_i = 120mV

2. For the cascaded arrangement shown in Fig Q2 calculate :

• i) The loaded voltage gain of each stage
• ii) The total gain of the system A_V and A_V1
• iii) The loaded current gain of each stage
• iv) The total current gain of the system.

3. List the advantages of negative feedback.

4. Derive an expression for input resistance of current series and current shunt feedback amplifier.

5. Negative feedback to be used to reduce noise from an amplifier by 90% i) what mast the percentage negative feedback to accomplish this, if the initial voltage gain is 50? ii) What will be the voltage gain with feedback.

6. Derive expression for Zi and Ai for a Darlington Emitter follower circuit.

7. Explain the need of a cascading amplifier. Draw and explain the block diagram of two stage cascade amplifier.

8. Write a note on cascade amplifier.

9. List the general characteristics of negative feedback amplifier.

10. A given amplifier arrangement has the following voltage gain AV₁ = 10, AV₂ = 20 and AV₃ = 40. Calculate the overall voltage gain and determine the total voltage gain in dBS.

11. For the voltage series feedback amplifier. Derive an expression for output impedance (Resistance).

MODULE 4

1.Derive an expression for frequency of oscillation of RC phase shift oscillator.

2. With a neat circuit diagram, explain the working of complementary class B power amplifier.

3. The following distortion readings are available for a power amplifier. D₂ = 0.2 , D₃ = 0.02, D₄ = 0.06 with I₁ = 3.3A and R_C = 4Ω
i) Calculate THD ii) Determine the fundamental power iii) calculate the total power

4. With a neat circuit diagram, explain the working of Hartley oscillator.

5. For a class B amplifier providing a 20V peak signal to a 16Ω load and a power supply of V_CC =30V determine the i/p power, o/p power and efficiency.

6. Explain the classification of power amplifier based on Q- point.

7. Show that maximum efficiency of class-B push pull amplifier (power amplifier) circuit is 78.54%.

8. Explain the classification of power amplifier with a neat circuit diagram and waveforms.

9. A class-B push pull amplifier operating with V_cc = 25V provides a 22V peak signal to 8Ω load. Calculate the circuit efficiency and power dissipated per transistor.

10. Draw the circuit of wein bridge oscillator and explain its operation.

11. With a neat circuit diagram and waveform, explain the working principal of crystal oscillator operating in series resonant mode. A crystal has the following parameters L = 0.334H, C=0.065pF and R = 5.5KΩ. Calculate its resonant frequency.

MODULE 5

1.Draw the circuit a fixed bias JFET amplifier and its equivalent circuit. Hence obtain the expression Z_in, Z_o and A_v.

2. A JFET has device parameter of g_mo = 10m℧ and I_pss = 12mA. When the device is suitably biased, the drain current was found to be 8mA. Determine: i) V_p ii) g_m iii) V_GS

3. Give the comparison of FET over BJT.

4. With a neat sketch, explain the construction and working principle of N-channel enhancement type MOSFET and also explain its static drain characteristics.

5. Obtain the expression for trans conductance gm of JFET.

6. For the voltage divider bias configuration shown in Fig Q6. Determine the value of R_s, if VD = 12V and V_GSQ = -2V.

7. With the help of neat diagram, explain the working and characteristics of N-channel JFET.

8. For a self bias JFET circuit, V_DD = +12V, R_D = 2.2KΩ, R_G = 1MΩ, R_S = 1KΩ, I_DSS = 8mA, V_p= -4 Volts. Determine the following parameters: i)V_GS ii) I_D iii) V_DS iv) V_s v) V_G vi) V_D

9. With neat sketches, explain the operation and characteristics of n-channel depletion type MOSFET.

10. Derive expression for V_GS, I_D, V_DS, V_D and V_S for a voltage divider bias circuit using FET.