What Happens When an IRQ or FIQ is Raised?

IRQ and FIQ Exceptions in ARM

Interrupts like IRQ (Interrupt Request) and FIQ (Fast Interrupt Request) are external exceptions that temporarily pause normal program execution to handle important events like a timer overflow or DMA transfer.

But they only occur if their mask bits (I and F) in the CPSR (Current Program Status Register) are cleared (set to 0).

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What Happens When an IRQ or FIQ Exception is Raised?

Step-by-Step Process:

Step	Description
1️⃣	Processor changes mode to IRQ or FIQ mode.
2️⃣	CPSR is saved into SPSR_<mode> (like spsr_irq or spsr_fiq).
3️⃣	PC (Program Counter) is saved into LR_<mode> (Link Register).
4️⃣	Interrupts are disabled: – IRQ disables only IRQ – FIQ disables both IRQ and FIQ
5️⃣	PC is set to vector table address: – IRQ = 0x18 – FIQ = 0x1C
6️⃣	Processor starts executing the ISR (Interrupt Service Routine) from the vector address.

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IRQ Exception Example (Normal Interrupt)

🔹 Used for general tasks like timers, UART, GPIO
🔸 Lower priority
🔹 Vector address: 0x18

IRQ Flow (from Figure 4.4):

1. CPU is in User mode.
2. IRQ occurs → CPU enters IRQ mode.
3. CPSR (user) is copied into SPSR_irq.
4. LR_irq stores return address (old PC).
5. IRQ bit in CPSR is set → further IRQs disabled.
6. PC is set to IRQ vector (0x18).
7. Software (ISR) handles the interrupt.
8. On return, SPSR_irq is restored to CPSR, and CPU goes back to user mode.

FIQ remains enabled during IRQ.

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FIQ Exception Example (Fast Interrupt)

🔹 Used for high-priority, low-latency tasks like DMA
🔸 Highest priority
🔹 Vector address: 0x1C

FIQ Flow (from Figure 4.5):

1. CPU is in User mode.
2. FIQ occurs → CPU enters FIQ mode.
3. CPSR is copied into SPSR_fiq.
4. LR_fiq stores return address.
5. Both IRQ and FIQ bits are set in CPSR → all interrupts disabled.
6. PC is set to FIQ vector (0x1C).
7. FIQ ISR runs, using banked registers r8–r14, avoiding context saving.
8. On return, restore state from SPSR_fiq, resume user mode.

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Enabling and Disabling IRQ/FIQ Interrupts

Interrupts can be manually enabled/disabled only in privileged mode using ARM assembly.

To Enable IRQ or FIQ:

MRS     r1, cpsr       ; Copy CPSR to r1
BIC     r1, r1, #0x80  ; Clear IRQ bit (bit 7) → enable IRQ
MSR     cpsr_c, r1     ; Write back to CPSR

• To enable FIQ, use #0x40 instead of #0x80.
• To enable both, use #0xC0.

To Disable IRQ or FIQ:

MRS     r1, cpsr       ; Copy CPSR
ORR     r1, r1, #0x80  ; Set IRQ bit → disable IRQ
MSR     cpsr_c, r1     ; Write back to CPSR