Cache memory is a small, fast memory placed between the CPU and main memory (RAM) to store frequently accessed data and instructions. It reduces access time, speeds up execution, and improves system performance.

Basic Architecture of Cache Memory

Cache memory has two main components:

Cache Controller

Cache Memory

1. Cache Memory (The actual data storage)

It consists of:

Directory Store (Tags): Stores the memory address (called cache-tag) of the data block in cache.

Data Section: Stores the actual data from memory.
Status Bits:
- Valid Bit: Tells if the cache line holds valid data.
- Dirty Bit: Tells if the cache line has been modified (written to) and needs to be written back to main memory.

Example:

Suppose address 0x500 contains value 42. The cache stores:

Cache-tag: 0x500
Data: 42

Valid bit: 1
Dirty bit: 0 (unchanged)

2. Cache Controller (The brain behind cache operation)

Manages all operations like searching, comparing tags, and fetching data.

Automatically checks for cache hit or miss.
Handles cache line fills (copying from RAM to cache).
Invisible to the application code—same C program works with or without cache.

How Cache Works – Step by Step

Step 1: Address Breakdown

When CPU wants data, the cache controller splits the address into:

Tag Field
Set Index Field → to find the correct line (or block)

Data Index Field → to select the correct word within the line

Step 2: Look Up Cache Line

Using Set Index, the cache controller looks at a cache line and checks:

Is the valid bit = 1?

Does the tag match?

If both yes → Cache Hit
If no → Cache Miss

Step 3: On Cache Hit

Data is directly given to CPU from cache (very fast).

Uses Data Index to extract the right word.

Step 4: On Cache Miss

Controller copies the full cache line from main memory (RAM) to cache.
Then sends the required word to CPU.

This process is called a cache line fill.

Types of Cache Architecture

Von Neumann Architecture

Shared memory bus for data and instructions.
Uses a Unified Cache (one cache for both).

Harvard Architecture

Separate buses for instructions and data.
Uses Split Cache:
- I-Cache → Instruction Cache
- D-Cache → Data Cache

ARM processors support both designs depending on model.