In this post, you will get the Computer Organization Previous year Solved question paper with answers. The question papers are of 18CS34, 17CS34, 15CS34
Computer Organization Previous Year Solved Question Paper.
MODULE -1
- List the steps needed to execute the machine instruction Add LOCA, RO in terms of transfers between the processor and the memory along with some simple control commends. Assume that the instruction itself is stored in the memory at location INSTR and that this address is initially in register PC. The first two steps might be expressed as:
- Transfer the contents of Register PC to register MAR.
- Issue a Read command to the memory and then wait until it has transferred the requested word into register MDR.What is performance measurement? Explain the overall SPEC rating for the computer in a program suit.
- Remember to include the steps needed to update the contents of PC from INSTR to INSTR+1 so that the next instruction can be fetched.
2. A] With relevant figure define the little Endian and big Endian assignments.
B]Consider a computer that has a byte addressable memory organized in 32 bit words according to the big Endian scheme. A program reads ASCII characters entered at a keyboard and store them in successive byte location starting at location 1000. Show the contents of the two memory words at locations 1000 and 1004 after the name “Johnson” has been entered. (ASCII codes J = 4 AH, o = 6 FH, h = 68 H, n = 6 EH, S = 73H)
C] Write about shift and rotate instruction with neat diagram and example of each.
3. A] Explain the Basic operational concepts of the computer with a neat diagram.
B] What is performance measurement? Explain the overall SPEC rating for the computer in a program suite.
C] Explain the following :
i) Byte addressability
ii) Big-endian assignment
iii) Little – endian assignment
4. A] show how the below expression will be executed in one address, two address and three address processors in an accumulator organization.
X = A × B + C × D
B] What is the effective address of the source operand in each of the following instructions. When the Register R1 and R2 of computer contain the decimal value 1200 and 4600?
- Load 20(R1),R5
- Move #3000, R5
- Store R5, 30(R1,R2)
- Add – (R2),R5
- Substract (R1)+,R5
C] Interpret the Subroutine Stack Frame with example.
5. A] With a neat block diagram discuss the basic operational concepts of a computer.
B] What is performance measurement? Explain overall SPEC rating for computer.
C] Explain Big-Endian, Little – Endian and assignment byte addressability.
6. A] what is an addressing mode ? Explain any three addressing mode with example.
B] Draw single bus structure, discuss about memory mapped I/O.
C] What is stack and queue ? Write the line of code to implement the same.
7. A] Define Addressing Mode. Give the details of different addressing modes.
B] Describe the basic operational concepts between the processor and memory.
8. A] What is Subroutine? How to pass parameters to subroutines? Illustrate with an example.
B] How to encode assembly instructions into 32-bit words? Explain with examples.
MODULE – 2
- A] With supporting diagram, explain the following with respect to interrupts:
i) Vectored interrupts
ii) Interrupt Nesting
iii) Simultaneous requests. (06 Marks)
B] Three devices A, B and C are connected to the bus of a computer. I/O transfers for all three devices use interrupt control. Interrupt nesting for devices A and B is not allowed, but interrupt requests from C may be accepted while either A or B is being services. Suggest different ways in which this can be accomplished in each of the following cases:
i) The computer has one interrupt request line.
ii) Two interrupt request line, INTR1 and INTR2 are available with INTR1 having higher priority. Specify when and how interrupts are enabled and disable in each case.
C] Illustrate the tree structure of USB with diagram.
2. A] With a neat diagram, explain the centralized arbitration and distributed bus arbitration scheme.
B] With neat timing diagram illustrate the asynchronous bus data transfer during an input operation. Use handshake scheme.
3. A] Illustrate a program that reads one line from the keyboard, stores it in memory buffer, and echoes it back to the display in an I/O interfaces.
B] What is an interrupt ? What are interrupt service routine and what are vectored interrupts ? Explain with example.
4. A] Demonstrate the DMA and its implementation and show how the data is transferred between memory and I/O device using DMA controller.
B] With a neat diagram, explains the general 8-bit parallel interface circuit.
C] Explain PCI bus data transfer in a computer system.
5. A] Define bus arbitration. Briefly explain the two approaches of bus arbitration.
B] Explain the following with respect to USB:
i) USB architecture ii) USB protocols.
6. A] With a neat block diagram, explain the general 8- bit parallel processing.
B] With a block diagram, Explain how the keyboard interfaced to processor.
C] Explain PCI bus.
7. A] Define Bus Arbitration. With diagrams, explain the centralized bus arbitration mechanism.
B] With the help of timing diagram, briefly discuss the main phases of SCSI bus involved in its operation.
8. A] With neat diagrams, explain how to interface printer to the processor.
B] Explain the following methods of handling interrupts from multiple devices.
i) Interrupt nesting/priority structure ii) Daisy chain method.
MODULE – 3
- A] Draw a diagram and explain the working of 16 Megabit DRAM chip configured as
2M × 8.
B] Describe organization of an 2M × 32 memory using 512K × 8 memory chips.
2. A] Discuss in detail the working of set associative mapped cache with two blocks per set with relevant diagram.
B] Define the following with respect to cache memory: (i) Valid bit, (ii) Dirty data, (iii) Stale data, (iv) Flush the cache.
C] A block-set associative cache consists of a total of 64 blocks divided into 4-blocks sets. The main memory contains 4096 blocks, each consisting of 128 words.
i) How many bits are there in a main memory address?
ii) How many bits are there in each of the TAG, SET and WORD fields?
3. A] Explain the organization of 1k × 1 memory chip.
B] With a neat figure explain the direct mapped cache in mapping function.
C] What is memory interleaving? Explain.
4. A] With a neat diagram briefly explain the internal organization of 2m × 8 dynamic memory chip.
B] illustrate cache mapping techniques.
C] Calculate the average access time experienced by a processor, if a cache hit rate is 0.88, miss penalty is 0.015 milliseconds and cache access time is 10 microseconds.
5. A] What is ‘ Locality of Reference’ ? Explain Direct mapping technique and set-associative mapping technique.
B] What is asynchronous DRAM ? With a neat diagram explain the internal organization of a 2M × 8 dynamic memory chip.
6. A] what is virtual memory ? With a diagram explain how virtual memory address translation take place.
B] write a note on:
i] Magnetic disk principle.
ii] Magnetic tape system.
7. A] Describe how to translate virtual address into physical address with diagram.
B] Draw and explain the internal organisation of 2M × 8 asynchronous DRAM chip.
8. A] Describe any two mapping functions in cache.
B] Describe the principles of magnetic disk.
MODULE – 4
- A] Convert the following pairs of decimal numbers to 5-bit signed 2’s complement binary numbers and add them. State whether or not overflow occurs in each case.
i) 5 and 10 ii) 14 and 11 iii) 5 and 7 iv) 10 and 13
B] Design the 16 bit carry look ahead adder using 4-bit adder. Also unite the expression for Ci + 1.
C] Draw the two n-bit number x and y to perform addition/subtraction.
2. A] With an example explain the Booths algorithm to multiply two signed operands.
B] Multiply each of the following pairs of signed 2’s complement number using the Booth algorithm. (A = multiplicand and B = multiplier).
i) A = 010111 and B = 110110
ii) A = 110011 and B = 101100
iii) A = 110101 and B = 011011
iv) A = 001111 and B = 001111
3. A] Perform the addition and subtraction of signed numbers :
i) +4 and -6
ii) -5 and -2
iii) +7 and -3
iv) +2 and +3
B] Explain 4 bit carry- look ahead adder with a neat diagram.
C] Perform bit pair recording for(+13) and (-6)
4. A] Perform Booth’s algorithm for signed numbers (-13) and (+11)
B] show and perform non restoring division for 3 and 8.
5. A] Explain with a neat block diagram, 4-bit carry look ahead adder.
B] Perform following operation on the 5-bit signed number using 2’s complement representation system. Also indicate whether over flow has occurred.
i) (-9) + (-7) ii) (+7) – (-8).
C] Explain the concept of carry save addition for the multiplication operation, M × Q = P for 4–bit operands with diagram and suitable example.
6. A] With a neat diagram, Explain IEEE standard for floating point numbers.
B] Perform multiplication for -13 and +09 using Booth’s Algorithm.
C] With a neat block diagram, explain circuit arrangement for binary division.
7. A] Perform the operations on 5 – bit signed numbers using 2’s complement system. Also indicate whether overflow has occurred.
i) (-10) + (-13) ii) (-10) – (-13) iii) (-2) + (-9).
B] Perform the multiplication of 13 and -6 using Booth algorithm and Bit – pair recoding method.
8. A] Perform the restoring division for 8 ÷ 3 by showing all the steps.
B] Explain the logic diagram of 4 – bit carry look ahead adder and its operations.
MODULE – 5
- A] Discuss with neat diagram, the single bus organization of the data path inside a processor.
B] Write the sequence of control steps required for single bus structure for each if the following instructions.
i) Add the contents of memory location NUM to register R1.
ii) Add the contents of memory location whose address is at memory location NUM to
register R1.
2. A] Discuss the microwave oven with neat block diagram.
B] Discuss the digital camera with neat block diagram.
3. A] Illustrate the sequence of operation required to execute the following instructions
Add ( R3) , R1
B] Explain the three bus organization of a data path with a neat diagram.
4. A] Compare and contrast the following :
i) Hard – wired control
ii) Microprogrammed control.
B] What is pipeline? Explain the 4 stages pipeline with its instruction execution steps and hardware organization.
5. A] What is pipelining ? Explain the Basic concept of pipeline performance with neat sketch.
B] Explain with neat diagram, micro – programmed control method for design of control unit and write the micro-routine for the instruction branch < 0.
C] Differential between hardwired and micro programmed control unit.
6. A] Briefly explain the block diagram of camera.
B] With a neat diagram, explain the structure of general purpose multiprocessors.
7. A] Draw and explain multiple bus organization along with its advantages.
B] Write down the control sequence for the instruction Add (R3) , R1 for single bus organization.
8. A] With block diagram, explain the general requirements and working of digital camera.
B] Write the control sequence for an unconditional branch instruction.