Analog and Digital Electronics Previous year Solved question paper

In this post, you will get the Analog and Digital Electronics Previous year Solved question paper with answers. The question papers are of 18CS33, 17CS/IS32, 15CS32

Analog and Digital Electronics Previous year Solved question paper

Module-1

1. Explain the construction, working, and characteristics of a Photodiode.
2. With Hysteresis characteristics explain the working of the Schmitt trigger circuit (Inverting).
3. With a neat circuit diagram and mathematical analysis explain the voltage divider bias circuit.
4. Explain the working of the R-2R ladder D to A converter.
5. Explain successive approximation A to D converter.
6. Show how the IC-555 timer can be used as Astable multivibrator.
7. Explain the working of an Astable multivibrator with necessary diagrams and expressions for frequency of oscillation, using timer IC 555.
8. Explain the construction and operation principle of N-channel JFET along with its Characteristics curves.
9. Explain self-bias circuit for JFET.
10. With neat figures and relevant waveforms, explain the working of the relaxation oscillator circuit using op-amp.
11. With a circuit diagram, explain the operation of a Relaxation oscillator.
12. What is MOSFET? Name its types. Explain the construction of n-channel E-MOSFET
13. Write the advantages of MOSFET over JFET.
14. Difference between MOSFET over JFET.
15. What are active filters? Explain active low pass filter.
16. Define: i) CMRR ii) Slew rate iii) PSRR iv) Bandwidth pertaining to OPAMP.
17. The figure shows a biasing configuration using DE-MOSFET. Given that the saturation Drain current is 8mA and the pinch-off voltage is -2V; determine the value of the Gate, source voltage, Drain current, and drain-source voltage.

Module-2

1. Using Q-M method, simplify the expression f(A, B, C, D) = Σ(0, 3, 5, 6, 7, 11, 14).
2. Explain about positive and negative logic prove that positive ‘OR’ is equal to negative ‘AND’.
3. list equivalence in positive and negative logic.
4. What are Hazards? Briefly describe about designing Hazard free circuit.
5. Explain the types of Hazards and its covers.
6. What are static hazards? How to design a hazard-free circuit? Explain with an example.
7. Give Sum-Of-Product (SOP) and Product-Of-Sum (POS) circuit for f(A, B, C, D) = Σm (6, 8, 9, 10, 11, 12, 13, 14, 15).
8. Find the minimum SOP and minimum POS for the following function using K-map. f(A, B, C, D) = Σm (1,2,3)+Σn(2,7,8,12,14,15).
9. What are the disadvantages of K-map method? How they are overcome in Quine Mccluskey method.
10. What is the MAP-Entered Variable method? Using MEV method simplify following function : f(A,B,C,D)=Σm (2,3,4,5,13,15)+dc(8,9,10,11)
11. With the help of flow chart explain how to determine minimum sum of products using Karnaugh map.
12. Design a logic circuit to provide an output when any two or three of four switches are closed.
13. Give the simplest logic circuit for following logic equation where d represents don’t care condition for following locations: F(A, B, C, D) = ∑m(7) + d (10, 11, 12, 13, 14, 15).
14. Simplify the following Boolean function by using Quine – McClusky method. F(A, B, C, D) = ∑m (0, 2, 3, 6, 7, 8, 10, 12, 13).
15. Simplify using QM method. F(A, B, C, D) = ∑m (1,2,8,10,11,14,15).
16. Using Q-M method simplify the following function F(A,B,C,D)=∑m(2,3,7,9,11,13)+∑d(1,10,15).
17. Discuss Briefly an HDL Implementation models.
18. With an example explain Petrik’s method.
19. A digital system is to be designed in which the months of the year is given as input in four bit form. the month january is represented as ‘0000’, February as ‘0001’, and so on. the output of the system should be ‘1’ corresponding to the input of the month containing 31 days or otherwise it is ‘0’. consider excess numbers in the input beyond ‘1011’ as don’t care conditions. For this system of four variables (A,B,C,D) find the following;
    • Boolean expression in ∑m and π m form.
    • Using K-map simplify in SOP form.
    • Implement using NAND-NAND gates.
20. Explain the concept of Duality in Digital circuits.
21. Explain the verilog program structure.
22. Prove that the duty cycle of a symmetrical waveform is 50%. An asymmetrical signal waveform is high for 2ms and low for 3ms. Find period, frequency, and duty cycle high.
23. Write a Verilog code for the figure in
    • Structural model
    • Dataflow model
    • Behavioral model

Module-3

1. What is a multiplexer? Design a 32:1 multiplexer using 16:1 MUX and one 2:1 multiplexer.
2. Implement following function using 8:1 MUX f(A,B,C,D)=∑m(1,2,5,6,9,12)
3. Design Hexadecimal (Binary) to ASCII code converter using suitable ROM. Give the connection diagram of ROM.
4. Explain Simulation and testing of digital circuits.
5. Show how using a 3 to 8 Decoder and multi-input OR Gates following Boolean Expressions can be realized simultaneously.
   • F(A, B, C) = ∑m (0, 4, 6)
   • F(A, B, C) = ∑m (1, 2, 3, 7)
   • F(A, B, C) = ∑m (0, 5)
6. Implement Y(A,B,C,D)=∑m(0,2,3,4,5,8,9,10,11,12,13,15) using 8 to 1 multiplexer.
7. Show how two 1 to 16 DEMUX can be connected to get 1 to 32 DEMUX.
8. Explain parity Generators and checkers using suitable examples.
9. What is Magnitude Comparator? Explain 1 bit magnitude comparator.
10. Write the truth table and logic circuit of a 1bit comparator.
11. What is PLA? Design seven segment Display using PLA.
12. What are the different types of PLD’s?
13. Differentiate between PAL and PLA. Realize following functions using PLA. Give PLA table and internal connection diagram for the PLA (use as many common terms as possible)
    • F₁(1,b,c,d)=∑_m(1,2,4,5,6,8,10,12,14)
    • F₂(a,b,c,d)=∑_m(2,4,6,8,10,11,12,14,15)
14. Design a priority encoder for a system with three inputs; the middle bit with highest priority encoding to 10, the MSB with next priority encoding to 11, while the LSB with least priority encoding to 01.
15. Write a Verilog code for a A-to-1 multiplexer using conditional assignment statement.
16. Differentiate combinational and sequential circuits.
17. What are Hazards in digital circuits? Explain different types of hazards.
18. Implement full subtractor using 3 to 8 decoder and NAND gates.

Module-4

1. Explain 4 bit serial in parallel out register.
2. Explain a 3 bit binary Ripple up counter. Give the block diagram, truth table and output waveforms.
3. Give a brief account an flip flop as finite state machine.
4. Explain the working of JK master slave Flip Flop along with implementation using NAND Gates.
5. Briefly describe about sequential logic circuit.
6. With block diagram, logic diagram, truth table and waveforms and timing diagram, Explain the working of Master-Slave JK Flip-Flop.
7. Design synchronous MOD – 6 counter with truth table and state diagram.
8. What is universal shift Register? Explain any one application of universal shift register with block diagram and truth table.
9. Write the comparison between Synchronous and Asynchronous counters.
10. Name and explain in short the four basic types of shift registers and draw a block diagram for each. Explain Serial In Serial Out (SISO) register
11. Mention the applicators of shift registers.
12. What is switch contact bounce? How to remove any contact bounce due to switch using SR latch.
13. How long it will take to shift the hexadecimal number ‘AB’ into 54/74164 (SIPO), If the clock is 5MHz?
14. Explain 4-bit sequence generator and programmable 4-bit sequence detector.
15. Explain the structure of VHDL program. With VHDL code for 4-bit parallel adder using full adder as component.
16. Explain the working of SR latch using NOR gates. Show how SR latch can be used for switch debouncing.
17. Differentiate between Latch and Flip Flop. Show how SR flip flop can be converted to D flip flop.
18. Using behavioral model write verilog HDL code for a ‘D’ flipflop with reset input.
19. Derive the characteristics equations for D, T, SR, and JK flipflop.
20. With an example explain the syntax of conditional signal assignment statement in VHDL.

Module-5

1. What is Shift Resister? Explain the working of 8-bit SISO shift register using SR flipflop.
2. With the help of state graph, State and transition tables and timing diagram explain the sequential parity checker.
3. What is a register? Explain how 4-bit register with data, load, clear, and clock input is constructed using D flip flops.
4. With block diagram explain the working of an n-bit parallel adder with an accumulator.
5. Explain digital clock with block diagram.
6. Design a 3 bit synchronous binary counter using JK flip flop.
7. Explain counter type A/D converter with diagram.
8. Mention different types of A/D converters and test its specifications.
9. Explain binary weighted resistor D/A converter. Mention its drawbacks.
10. Describe about successive approximation type ADC.
11. What is the resolution of a 12 bit D/A converter which uses a binary ladder, if the full scale output is +10V?
12. What is the resolution of a 9-bit D/A converter which uses a ladder network? If the full-scale output voltage of this converter is +5v, what is resolution in volts?
13. Explain 5 bit Resistive divider with diagram.
14. Explain with neat diagram the working principle of Digital clock.
15. Explain the terms Accuracy and Resolution for D/A converter with example.
16. Explain with Block diagram the operation of successive approximation converter.
17. What do you mean by lockout condition in counters? Using JK flipflops design self correcting mod-6 counter.
18. Draw the schematic for a 4-bit binary ladder and explain how digital to analog conversion is achieved using it.
19. Design a random counter using T flip flops whose transition graph is shown in fig.1

20. Differentiate between Moore and Mclay machines. Analyze following Moore sequential circuit for an input sequence of X=01101 and draw the timing diagram.

Analog and Digital Electronics Previous year Solved question paper

In this post, you will get the Analog and Digital Electronics Previous year Solved question paper with answers. The question papers are of 18CS33, 17CS/IS32, 15CS32

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